A growing number of electrical devices, which may be ICs or embedded cores within ICs, are being tested using test compression architectures (TCA), such as Mentor's TestKompress™ embedded deterministic test technology, incorporated herein by reference. Fundamentally a TCA consists of three elements, a decompressor circuit, a parallel scan path arrangement, and a compactor circuit. The decompressor circuit receives compressed input data from one or more inputs from a tester, decompresses the compressed input data into parallel stimulus patterns that are input to parallel scan paths. The compactor circuit receives parallel response patterns that are output from the parallel scan paths, compacts the response patterns down to one or more compressed data outputs that are input to the tester. A first advantage of TCAs is that they allow a large number of shorter length parallel scan paths to be accessed using only a small number of compressed data inputs and compressed data outputs. A second advantage of TCAs is that they reduce the amount of test data that needs to be transmitted between the tester and device under test, since the test data is compressed. The present disclosure provides methods and apparatuses for enabling a device TCA to be accessed for testing using either a parallel bus of compressed input and compressed output test signals or a serial bus of a compressed input and compressed output test signals.
FIG. 1 illustrates an example of device 100 containing a test compression architecture (TCA) 102. The TCA 102 is interfaced to an external tester via a parallel bus of N compressed data input (CI) signals, a parallel bus of N compressed data output (CO) signals, a scan clock (SC) input, and a scan enable (SE) input. While TCAs may use only a single CI input and a single CO output, it is more common in a device manufacturing test environment to use a bus of parallel CI inputs and a bus of parallel CO outputs, since this reduces device test time. The TCA 102 comprises a decompressor 104, a compactor 106, and parallel scan paths 108. The TCA 102 may also include a clock selector (CS) 110 to allow the parallel scan paths to be clocked by the devices functional clock (FC) at times when the parallel scan paths are capturing response data. The decompressor has inputs coupled to the CI, SC and SE inputs and outputs coupled to the scan inputs (SI) of the parallel scan paths 108. The compactor has inputs coupled to the scan outputs (SO) of parallel scan paths 108 and an output coupled to the CO output. The parallel scan paths 108, in addition to the SI inputs and SO outputs, have inputs coupled to the SC and SE inputs, inputs coupled to response outputs from combinational logic, and outputs coupled to stimulus inputs to combinational logic, as shown in FIG. 3. If the CS 110 is used, the SE input will control it to pass the SC signal to the parallel scan paths 108 during shift operations and to pass the FC signal to the parallel scan paths 108 during capture operations.
FIG. 2 illustrates the operational states 202 and 204 of the TCA during test. In state 202 when the SE input is low and an SC input occurs the parallel scan paths capture response data from the combinational logic and the decompressor is reset to a known state. If CS 110 is used, the logic low on SE will select the FC signal to clock the parallel scan paths in state 202. In state 204 when the SE input is high and SC inputs occur the decompressor 104 decompresses the data input on CI inputs into parallel scan inputs (SI) that are shifted into the parallel scan paths, and the compactor 106 inputs and compacts the parallel scan outputs (SO) from the parallel scan paths into compressed outputs that are output on the CO outputs. If CS 110 is used, the logic high on SE will select the SC signal to clock the parallel scan paths in state 204. The TCA will remain in state 204 until the compressed input to the parallel scan paths and the compressed output from the scan paths is complete. As can be seen the capture and shift operation states of the TCA is similar to the capture and shift operation states of conventional scan paths, with the exception that the TCA includes the additional operations of decompressing the data input on the CI inputs to produce the scan inputs (SI) to the parallel scan paths and compressing the scan outputs (SO) from the parallel scan paths into a compressed form that can be output on the CO outputs.
While the example of FIG. 2 shows SE being low in state 202 and high in state 204, the logic levels of SE for these states could be reversed if desire.
Most known decompressors 104 utilize a linear feedback state machine (LFSM) in conjunction with a phase shifter circuit to produce the output patterns that are applied to the SI inputs of the parallel scan paths 108. In the referenced Mentor TestKompress™ technology, the LFSM is referred to as a ring generator which is a particular type of linear feedback shift register. The ring generator receives the CI input data and, in response, produces pseudo random input patterns to the phase shifter. The phase shifter responds to the pseudo random input patterns to output stimulus input (SI) patterns to the parallel scan paths. The CI input data modifies the output patterns from the ring generator to allow the phase shifter to produce the desired stimulus pattern input to the parallel scan paths.
Most known compactors 106 utilize XOR gating trees that input the scan outputs (SO) from the parallel scan paths and compress them, via XOR gating, into compacted signals that can be output on the CO outputs. While simple compactors may only use XOR gating trees, more sophisticated compactors, such as the compactor used the reference Mentor TestKompress™ technology, may use XOR gating trees in combination with masking circuitry to allow masking off unknown scan outputs (SO) from the parallel scan path scan to prevent the unknown scan outputs from corrupting the compacted signals output on the CO outputs. If the compactor contains masking circuitry it can receive masking data (MD) from the decompressor 104 and control from SC and SE to load the masking data, as shown in dotted line in FIG. 1.
FIG. 4 illustrates an example of a device 402 with a TCA 102 being connected to an external parallel tester 404 via parallel CI (PCI), parallel CO (PCO), SC, and SE interface signals to allow TCA test patterns to be applied to the device. This example is typical of how the device manufacturer would test the device.
FIG. 5 illustrates the tester 404 of FIG. 4 operating the SC and SE signals to perform a TCA scan cycle. The scan cycle includes a capture operation 502 that Captures response data and Resets the decompressor to a starting seed state, i.e. state 202 of FIG. 2, followed by a shift operation 504, whereby the tester inputs PCI data to the TCA decompressor 104 and receives PCO data from the TCA compactor 106, i.e. state 204 of FIG. 2. The response capture and decompressor reset operation is indicated in this and following timing diagrams as CR. The shift operation 504 continues until the parallel scan paths are filled with stimulus data and emptied of response data. The scan cycle of FIG. 5 repeats 508 until all the TCA test patterns have been applied and the TCA test is complete.
FIGS. 4 and 5 have illustrated an example of how a tester 404 can access a device's TCA 102 for testing when a connection can be made between the tester and the device's TCA interface. As seen in FIG. 4 the connection between the tester and device TCA requires a direct connection for the PCI signals, a direct connection for the SC signal, a direct connection for the SE signal and a direct connection for the PCO signal.
The present disclosure, as will described in detail below, identifies how to modify a TCA to allow the TCA to be selectively accessed using parallel CI and parallel CO signals coupled to high cost parallel testers as shown in regard to FIG. 4 or using serial CI (SCI) and serial CO (SCO) signals coupled to low cost serial testers. Additionally, the disclosure identifies how to test a device TCA using low cost JTAG controllers.